Advanced Semiconductor Device&Circuit Laboratory
차세대 반도체 소자 및 회로 연구실
2024
102. Dongyeol Ju, Minsuk Koo*, Sungjun Kim*, "Implementation of 8-bit reservoir computing through volatile ZrOx-based memristor as a physical reservoir", Nano Energy, Vol. 128, Part B, pp. 109958, Sep. 2024.
101. Gwang-Eun Choi, Min-Joon Kim, Ra-Yeong Park, Yoon Kim*, and Dong-Wook Park*, "InGaZnO Thin-Film Transistor-based pH Sensor with Parylene-C Gate Dielectric", Journal of Sensor Science and Technology, Vol 33, No.5, Sep. 2024.
100. Dongyeol Ju, Yongjin Park, Minseo Noh, Minsuk Koo*, Sungjun Kim*, "HfAlOx-based ferroelectric memristor for nociceptor and synapse functions", The Journal of Chemical Physics, Vol. 161, Iss. 8, pp. 084706, Aug. 2024.
99. Eunjin Lim, Dahye Kim, Jongmin Park, Minsuk Koo*, Sungjun Kim*, "Recent advances in the mechanism, properties, and applications of hafnia ferroelectric tunnel junctions", Journal of Physics D: Applied Physics, Vol. 57, Iss. 47, pp. 473001, Aug. 2024.
98. Gyeongpyo Kim, Seoyoung Park, Minsuk Koo*, Sungjun Kim*, "Oxygen-Plasma-Treated Al/TaOX/Al Resistive Memory for Enhanced Synaptic Characteristics", Biomimetics, Vol. 9, Iss. 9, pp. 578, Jul. 2024.
97. Seonjeong Lee, Yifu Huang, Yao-Feng Chang, Seungjae Baik, Jack C Lee, Minsuk Koo*, "Enhancing simulation feasibility for multi-layer 2D MoS 2 RRAM devices: reliability performance learnings from a passive network model", Physical Chemistry Chemical Physics, Vol. 26, Iss. 31, pp. 20962-20970, Jul. 2024.
96. Swarup Biswas, Hyo-won Jang, Yongju Lee, Hyojeong Choi, Yoon Kim*, Hyeok Kim*, Yangzhi Zhu*, "Recent advancements in implantable neural links based on organic synaptic transistors", Exploration, 20220150, Apr.2024.
95. Dongyeol Ju, Sungjoon Kim, Kyungchul Park, Jungwoo Lee, Minsuk Koo*, Sungjun Kim*, "Realization of Multiple Synapse Plasticity by Coexistence of Volatile and Nonvolatile Characteristics of Interface Type Memristor", ACS Applied Materials & Interfaces, Vol. 16, Iss. 19, pp. 24929-24942,
Apr. 2024.
94. Won Joo Lee, Boram Kim, Minsuk Koo*, Yoon Kim*, "Three-Dimensional Resistive Random-Access Memory Based on Stacked Double-Tip Silicon Nanowires for Neuromorphic Systems", ACS Applied Electronic Materials, Vol. 6, Iss. 4, pp. 2232-2241, Apr. 2024.
93. Ah-Hyun Hong , Yu Jung Park , Jung-Hwa Seo , Yoon Kim*, Dong-Wook Park* , "Parylene-C-based flexible organic thin-film transistors and their reliability improvement using SU-8 passivation", JVSTB, Vol 42, No.3, May.2024.
92. Hyogeun Park, Dongyeol Ju, Chandreswar Mahata, Andrey Emelyanov, Minsuk Koo*, Sungjun Kim*, "Long‐and Short‐Term Memory Characteristics Controlled by Electrical and Optical Stimulations in InZnO‐Based Synaptic Device for Reservoir Computing", Advanced Electronic Materials, Mar. 2024
91. Jun Hui Park∇, Jung Nam Kim∇, Seonhaeng Lee, Gang-Jun Kim, Namhyun Lee, Rock-Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim*, "Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning", IEEE Access, pp.1-1, Jan.2024.
2023
90. Dongyeol Ju, Minsuk Koo*, Sungjun Kim*, "Improved Resistive Switching Characteristics and Synaptic Functions of InZnO/SiO2 Bilayer Device", Materials, Vol. 16, Iss. 23, Nov. 2023
89. Yongju Lee, Swarup Biswas, Minsuk Koo, Hyeok Kim*, "Recent Development in Biocompatible Biosensors", Journal of Sensor Science and Technology, Vol.32, Iss. 6, pp.403-411, Nov. 2023.
88. Jihyung Kim, Subaek Lee, Sungjoon Kim, Seyoung Yang, Jung-Kyu Lee, Tae-Hyeon Kim, Muhammad Ismail, Chandreswar Mahata, Yoon Kim, Woo Young Choi,* Sungjun Kim*, "Synaptic Characteristics and Vector-Matrix Multiplication Operation in Highly Uniform and Cost-Effective Four-Layer Vertical RRAM Array",Advanced Functional Materials, 2310193, Nov.2023.
87. Jaesung Kim, Jung Nam Kim, Yoon Kim, Sungmin Hwang*, Minsuk Koo*, "Design of a 180 nm CMOS Neuron Circuit with Soft-Reset and Underflow Allowing for Loss-Less Hardware Spiking Neural Networks", Advanced Intelligent Systems, 2300460, Nov.2023.
86.Chan-Gi Yook, Jung Nam Kim, Yoon Kim, Wonbo Shim, "Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications", MDPI Micromachines, 14(9), 1753, Sep.2023.
85. Dongyeon Kang, Wonjung Kim, Jun Tae Jang , Changwook Kim, Jung Nam Kim, SungJin Choi, Jong-Ho Bae, Dong Myong Kim, Yoon Kim*, Dae Hwan Kim*, "Short- and Long-term Memory Based on a Floating-Gate IGZO Synaptic Transistor", IEEE Access, pp.1-1, Feb.2023.
2022
84. Sungju Choi∇, Ga Won Yang∇, Sangwon Lee, Jingyu Park, Changwook Kim, Jun Park , Hyun-Seok Choi, Namhyun Lee, Gang-Jun Kim, Yoon Kim, Myounggon Kang, Changhyun Kim, Jong-Ho Bae*, Dae Hwan Kim*, "Fowler–Nordheim Stress-Induced Degradation of Buried-Channel-Array Transistors in DRAM Cell for Cryogenic Memory Applications", IEEE Transactions on Electron Devices, Vol.70, pp.48-52, Nov.2022.
83. Tae Jun Yang∇, Je-Hyuk Kim∇, Chang Il Ryoo, Seung Joo Myoung, Changwook Kim, Ju Heyuck Baeck, Jong-Uk Bae, Jiyong Noh, Seok-Woo Lee, Kwon-Shik Park, Jeom-Jae Kim, Soo-Young Yoon, Yoon Kim*, Dae Hwan Kim*, "Analysis of Drain-Induced Barrier Lowering in InGaZnO Thin-Film Transistors", IEEE Transactions on Electron Devices, Vol. 70, pp.121-126, Nov.2022.
82. Jongmin Park, Tae-Hyeon Kim*, Osung Kwon, Muhammad Ismail, Chandreswar Mahata, Yoon Kim, Sangbum Kim, Sungjun Kim*, "Implementation of convolutional neural network and 8-bit reservoir computing in CMOS compatible VRRAM", Nano Energy, Vol 104, Part B, 107886, Dec.2022.
81. JO-EUN KIM ,BORAM KIM, HUI TAE KWON, JAESUNG KIM , KYUNGMIN KIM, DONG-WOOK PARK*, YOON KIM*,"Flexible Parylene C-Based RRAM Array for Neuromorphic Applications", IEEE Access, Vol. 10, pp. 109760 - 109767, 2022.
80. Seungwon Go, Shinhee Kim, Jae Yeon Park, Dong Keun Lee, Hyung Ju Noh, So Ra Park , Yoon Kim, Dae Hwan Kim, Sangwan Kim*, "Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)", Solid State Electronics, 108483 (198), Dec. 2022.
79. JUNG NAM KIM, JAE HONG LEE, JO EUN KIM, SUCK WON HONG, MINSUK KOO*, YOON KIM*, "NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory", IEEE Journal of the Electron Devices Society, Vol.10, pp. 813-820, Sep. 2022.
78. Geun Ho Lee, Tae-Hyeon Kim, Min Suk Song, Jin woo Park, Sung joon Kim, Kyung ho Hong, Yoon Kim, Byung-Gook Park*, Hyung jin Kim*, "Effect of weight overlap region on neuromorphuc systems with memristive synaptic devices," Chaos, Solitions and Fractals, 157, 111999, 2022.
77. Hyun-Seok Choi, Jihye Lee, Boram Kim, Jaehong Lee, Byung-Gook Park, Yoon Kim*, and Suck Won Hong*, "Highly-packed self-assembled graphene oxide film-integrated resistive randomaccess memory on a silicon substrate for neuromorphic application," Nanotechnology, Vol. 33, 435201, Aug. 2022.
2021
76. Eunseon Yu, Amogh Agrawal, Dongqi Zheng, Mengwei Si, Minsuk Koo, D. Ye Peide, Sumeet Kumar Gupta, and Kaushik Roy*. "Ferroelectric FET Based Coupled-Oscillatory Network for Edge Detection", IEEE Electron Device Letters, Vol. 42, Iss. 11, pp. 1670-1673, Oct. 2021.
75. S. Kwon, Y. Kim, M. Kang*, S. Kim*, "Comparison of synaptic properties considering dopant concentration and device operation polarity in Cu/SiN/SiO2/p-Si devices for neuromorphic system," Applied Surface Science, Vol. 563, 150101, Oct. 2021.
74. U. Rasheed, H. Ryu, C. Mahata, R. A. Khalil, M. Imran, A, M. Rana, F. Kousar, B. Kim, Y. Kim, S. Cho, F. Hussain*, and S. Kim*, "Resistive switching characteristics and theoretical simulation of a Pt/a- Ta2O5/TiN synaptic device for neuromorphic applications," Journal of Alloys and Compounds, Vol. 877, 160204, Oct. 2021.
73. Ji-Hoon Ahn, Hyun-Seok Choi, Jung Nam Kim, Byung-Gook Park, Sungjun Kim, Jaehong Lee*, and Yoon Kim*, "On-Chip Adaptive Matching Learning for Adaptive Neuromorphic Systems," Solid State Electronics, 108177 (186), Sep. 2021.
72. Amogh Agrawal, Mustafa Ali, Minsuk Koo, Nitin Rathi, Akhilesh Jaiswal, Kaushik Roy*, "IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks", IEEE Solid-State Circuits Letters, Vol. 4, pp. 137-140,
Jul. 2021.
71. Jun Park, Namhyun Lee, Gang-Jun Kim, Hyun-Seok Choi, Dae Hwan Kim, Changhyun Kim, Myounggon Kang*, and Yoon Kim*, "Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature," IEEE Electron Device Letters, Vol. 42, No. 5, pp. 653-656, Apr. 2021.
70. Ji-Ho Ryu∇, Boram Kim∇, Fayyaz Hussain c, Chandreswar Mahata a, Muhammad Ismail d, Yoon Kim*, and Sungjun Kim*, "Bio-inspired synaptic functions from a transparent zinc-tin-oxide-based memristor for neuromorphic engineering," Applied Surface Science, vol. 544, 145796, Apr. 2021.
69. Je-Hyuk Kim, Jun Tae Jang, Jong-Ho Bae, Sung-Jin Choi, Dong Myoung Kim, Changwook Kim, Yoon Kim*, and Dae Hwan Kim*, "Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors," MDPI micromachine, Vol. 12, 327, Mar. 2021.
2020
68. Jang, Jun Tae; Donguk, Kim; Choi, Woo Sik; Choi, Sung-Jin; Kim, Dong Myong; Kim, Yoon*; Kim, Dae Hwan*, "One Transistor-Two Memristor Based on Amorphous Indium-Gallium-Zinc-Oxide for Neuromorphic Synaptic Devices," ACS Applied Electronic Materials, vol. 2, pp. 2837-2844, 2020.
67. Jinju Lee∇, Ji-Ho Ryu∇, Boram Kim, Fayyaz Hussain, Chandreswar Mahata, Eunjin Sim, Muhammad Ismail, Yawar Abbas, Haider Abbas, Dong Keun Lee, Min-Hwi Kim, Yoon Kim, Changhwan Choi, Byung-Gook Park, and Sungjun Kim*, "Synaptic Characteristics of Amorphous Boron Nitride-Based Memristors on a Highly Doped Silicon Substrate for Neuromorphic Engineering," ACS Applied Materials & Interfaces, vol. 12, pp. 33908-33916, 2020.
66. Minsuk Koo, MR Pufall, Yong Shim, AB Kos, Gyorgy Csaba, Wolfgang Porod, WH Rippard, Kaushik Roy*, ”Distance Computation Based on Coupled Spin-Torque Oscillators: Application to Image Processing”, Physical Review Applied, Vol. 14, Iss. 3, pp.034001, Sep. 2020.
65. Boram Kim, Hyun-Seok Choi, and Yoon Kim*, "A Study of Conductance Update Method for Ni/SiNx/Si Analog Synaptic Device," Solid State Electronics, Vol. 171, 107772, Sep. 2020.
64. Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Chandreswar Mahata, Teresa Oh, Yoon Kim*, and Sungjun Kim*, "Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering," IEEE Access, Vol. 8, pp. 130678-130686, 2020.
63. Hyun-Seok Choi, Hyungjin Kim, Hong-Ho Lee, Byung-Gook Park, and Yoon Kim*, "AND Flash Array Based on Charge Trap Flash for Implementation of Convolutional Neural Networks," IEEE Electron Device Letters, Vol. 41, No. 11, pp. 1653-1656, Jul. 2020.
62. Seok Jung Kang, Jeong-Uk Park, KyungJin Rim, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim*, "Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor," Journal of Nanoscience and Nanotechnology, Vol. 20, No. 7, pp. 4409-4413, July. 2020.
61. Ye Sung Kwon, Seong-Hyun Lee, Yoon Kim, Garam Kim, Jang Hyun Kim, and Sangwan Kim*, "Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon," Journal of Nanoscience and Nanotechnology, Vol. 20, No. 7, pp. 4182-4187, July. 2020.
60. Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika Liyanagedera, Abhronil Sengupta, Kaushik Roy*, ”Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May. 2020.
59. Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy*, ”sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol 67,
Iss 8, pp. 2546 - 2555, Mar. 2020.
2019
58. Hyun-Seok Choi, Yu Jeong Park, Jonh-Ho Lee, and Yoon Kim*, "3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application," MDPI Electronics, 9(1), 57, Dec. 2019.
57. Seunghyun Yun, Jeongmin Oh, Seokjung Kang, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim*, “F-shaped tunnel field-effect transistor (TFET) for the low-power application,” Micromachines, Vol. 10, No. 11, p. 760 (1-10), Nov. 2019.
56. Won Joo Lee, Hui Tae Kwon, Hyun-Seok Choi, Daehoon Wee, Yu Jeong Park, Boram Kim, and Yoon Kim*, "Vertical Tunnel Field-Effect Transistor with Polysilicon Layer," Journal of Nanoscience and Nanotechnology, Vol. 19, No. 10, pp. 6722-6726, Oct. 2019.
55. Aayush Ankit*, Minsuk Koo*, Shreyas Sen, Kaushik Roy*, ”Powerline Communication for Enhanced Connectivity in Neuromorphic Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, Iss. 8, pp. 1897 - 1906, Aug. 2019.
54. Hui Tae Kwon, Won Joo Lee, Hyun-Seok Choi, Daehoon Wee, Yu Jeong Park, Boram Kim, Sungjun Kim, Byung-Gook Park, and Yoon Kim*, "Resistive Random-Access Memory with a-Si/SiNx Double-Layer," Solid State Electronics, Vol. 158, pp. 64-69, Aug. 2019.
53. Jaehong Lee, Byung-Gook Park, and Yoon Kim*, "Implementation of Boolean Logic Functions in Charge Trap Flash for In-memory Computing," IEEE Electron Device Letters, Vol. 40, No. 9, pp. 1358-1361, Jul. 2019.
52. Daehoon Wee, Hui Tae Kwon, Won Joo Lee, Hyun-Seok Choi, Yu Jeong Park, Boram Kim, and Yoon Kim*, "U-shaped Reconfigurable Field-effect Transistor," Journal of Semiconductor Technology and Science, Vol. 19, No. 1, pp. 63-68, Feb. 2019.
51. Daehoon Wee, Hui Tae Kwon, Hyun-Seok Choi, Boram Kim, and Yoon Kim*, "Current Conveyor-based Neuron Circuit for Neuromorphic System Implementation," Journal of The Institute of Electronics and Information Engineers, Vol. 56, No. 2, pp. 53-57, Feb. 2019.
2018
50. Yu Jeong Park, Hui Tae Kwon, Boram Kim, Won Joo Lee, Dae Hoon Wee, Hyun-Seok Choi, Byung-Gook Park, Jong-Ho Lee, and Yoon Kim*, "Three-Dimensional Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks," IEEE Transactions on Electron Devices, Vol. 66, No. 1, pp. 420-427, Dec. 2018.
49. Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Ying-Chen Chen, Yao-Feng Chang, Muhammad Ismail, Yoon Kim, Kyung-Chang Ryoo, and Byung-Gook Park*, "Concurrent events of memory and threshold switching in Ag/SiNx/Si devices," Journal of Vacuum Science&Technology B, Vol. 36, 051203, Sep. 2018.
48. Hyun-Seok Choi, Dae-Hoon Wee, Hyungjin Kim, Sungjun Kim, Kyung-Chang Ryoo, Byung-Gook Park, and Yoon Kim*, "3-D Floating-Gate Synapse Array With Spike-Time-Dependent Plasticity," IEEE Transactions on Electron Devices, Vol. 65, No. 1, pp. 101-107, Jan. 2018.
2017
47. Myounggon Kang and Yoon Kim*, "Natural Local Self-Boosting Effect in 3D NAND Flash Memory," IEEE Electron Device Letters, Vol. 38, No. 9, pp. 1236-1239, Sep. 2017.
46. Won Joo Lee, Hui Tae Kwon, Dae Hoon Lee, and Yoon Kim*, "Tunnel Fin Field-Effect Transistor with Epitaxial Silicon and Asymmetric Gate," Journal of Nanoscience and Nanotechnology, Vol. 17, No. 10, pp. 7087-7092, Oct. 2017.
45. Won Joo Lee, Sang Wan Kim*, and Yoon Kim*, "Reconfigurable U-Shaped Tunnel Field-Effect Transistor," IEICE Electronics Express, Vol. 14,
No. 20, Oct. 2017.
44. Yoon Kim, Il Han Park, Hui Tae Kwon, Daehoon Wee, and Byung-Gook Park*, "Three-dimensional AND flash memory," Electronics Letters,
Vol. 53, No. 11, pp. 739-741, May 2017.
43. Yonghwan Son, Yoon Kim*, and Myounggon Kang*, "Characterization of Oxide Trap Density with the Charge Pumping Technique in Dual-layer Gate Oxide," IEICE Electronics Express, Vol. 8, No. 8, Apr. 2017.
42. Sungjun Kim, Yao-Feng Chang, Min-Hwi Kim, Tae-Hyeon Kim, Yoon Kim, and Byung-Gook Park*, "Self-Compliant Bipolar Resistive Switching in SiN-Based Resistive Switching Memory," Materials, Vol. 10, No. 5, Apr. 2017.
41. Yonghwan Son, Yoon Kim*, and Myounggon Kang*, "Investigation of Capture and Emission Dependence between Individual Traps from Complex Random Telegraph Signal Noise Analysis," IEICE Electronics Express, Vol. 14, No. 2, Jan. 2017.
2016
40. Yoon Kim and Myounggon Kang*, "Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory," IEEE Electron Device Letters, Vol. 37, No. 12, pp. 1566-1569, Dec. 2016.
39. Hui Tae Kwon, Sang Wan Kim, Won Joo Lee, and Yoon Kim*, "A Recessed-Channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain," Journal of Semiconductor Technology and Science, Vol. 16, No.5, Oct. 2016.
38. Jongwook Jeon, Yoon Kim*, and Myonggon Kang*, "Investigation of the induced gate noise of nanoscale MOSFETs in the very high frequency region," Semiconductor Science and Technology, Vol. 31, pp. 065004-, Apr. 2016.
2015
37. Dong Hua Li, Wandong Kim, Won Bo Shim, Se Hwan Park, Yoon Kim, Gil Sung Lee, Doo-Hyun Kim, Jang-Gn Yun, Seongjae Cho, and Byung-Gook Park*, "Effects of Gate/Blocking oxide energy barrier on memory characteristics in charge trap flash memory cells,"Nanoscience and Nanotechnology Letters, Vol. 7, No. 7, pp. 594-598, Jul. 2015.
36. Yoon Kim, Won Bo Shim, and Byung-Gook Park*, "Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory," Japanese Journal of Applied Physics, Vol. 54, No. 6, pp. 064201-, Jun. 2015
2014
35. Yoon Kim, Myounggon Kang*, "Predictive Modeling of Channel Potential in 3-D NAND Flash Memory," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp. 3901-3904, Nov. 2014.
34. Yoon Kim, Joo Yun Seo, Sang-Ho Lee, and Byung-Gook Park*, "A new programming method to alleviate the program speed variation in three-dimensional stacked array NAND flash memory," Journal of Semiconductor Technology and Science, Vol. 14, No. 5, pp. 566-571, Oct. 2014.
33. Joonho Gil, Ji-Hoon Kim, Chun Suk Kim, Chulhyun Park, Jungsu Park, Hyejin Park, Hyeji Lee, Sung-Jae Lee, Young-Ho Jang, Minsuk Koo, Joon-Min Gil, Kwangseok Han, Yong Won Kwon, Inho Song, ”A Fully Integrated Low-Power High-Coexistence 2.4-GHz ZigBee Transceiver for Biomedical and Healthcare Applications”, IEEE Transactions on Microwave Theory and Techniques, Vol. 62, Iss. 9, pp. 1879 - 1889, Aug. 2014.
32. Joo Yun Seo, Yoon kim, and Byung-Gook Park*, "New program inhibition scheme for high boosting efficiency in three-dimensional NAND array," Japanese Journal of Applied Physics: Rapid Communications, Vol. 53, No. 7, pp. 070304-1-070304-3, Jun. 2014.
2013
31. Yoon Kim, Myounggon Kang, Se Hwan Park, and Byung-Gook Park*, "Three-Dimensional NAND flash memory based on single-crystalline channel stacked array," IEEE Electron Device Letters, Vol. 34, No. 8, pp. 990-992, Aug. 2013.
2012
30. Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, and Byung-Gook Park*, "Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory," Solid-State Electronics, Vol. 78, No. , pp. 34-38, Dec. 2012.
29. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, and Byung-Gook Park*, "Variation of threshold voltage and ON-cell current caused by cell gate length fluctuation in virtual Source/Drain NAND flash memory," Japanese Journal of Applied Physics: Regular Papers, Vol. 51, No. 7, pp. 074301-1-074301-6, Jun. 2012.
28. Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Hyungjin Kim, and Byung-Gook Park*, "Novel three dimensional (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer)," IEICE Transactions on Electronics, Vol. E95-C, No. 5, pp. 837-841, May. 2012.
27. Won Bo Shim, Seongjae Cho, Jung Hoon Lee, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Se Hwan Park, Wandong Kim, Jungdal Choi, and Byung-Gook Park*, "Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory," IEEE Transactions on Nanotechnology, Vol. 11, No. 2, pp. 307-313, Mar. 2012.
26. Yoon Kim, Jang-Gn Yun, Se Hwan Park, Wandong Kim, Joo Yun Seo, Myounggon Kang, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park*, "Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline STacked ARray," IEEE Transactions on Electron Devices, Vol. 59, No. 1, pp. 35-45, Jan. 2012.
2011
25. Dong Hua Li, Yoon Kim, Doo-Hyun Kim, Gil Sung Lee, and Byung-Gook Park*, "Comparative Analysis of Trap-Based Progrom/Erase Behaviors with Different Tunnel Barriers," Journal of Nanoscience and Nanotechnology, Vol. 11, No. 12, pp. 10535-10538, Dec. 2011.
24. Jang-Gn Yun, Garam Kim, Joung-Eob Lee, Yoon Kim, Won Bo Shim, Jong-Ho Lee, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park*, "Single-Crystalline Si STacked ARray (STAR) NAND flash memory," IEEE Transactions on Electron Devices, Vol. 58, No. 4, pp. 1006-1014, Apr. 2011.
23. Seongjae Cho, Won Bo Shim, Yoon Kim, Jang-Gn Yun, Jong Duk Lee, Hyungcheol Shin, Jong-Ho Lee, and Byung-Gook Park*, "A Charge Trap Folded NAND Flash Memory Device With Band-Gap-Engineered Storage Node," IEEE Transactions on Electron Devices, Vol. 58, No. 2, pp. 288-295, Feb. 2011.
2010
22. Wandong Kim, Jung Hoon Lee, Jang-Gn Yun, Seongjae Cho, Dong Hua Li, Yoon Kim, Doo-Hyun Kim, Gil Sung Lee, Se Hwan Park, Won Bo Shim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park*, "Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance," IEEE Electron Device Letters, Vol. 31, No. 12, pp. 1374-1376, Dec. 2010.
21. Doo-Hyun Kim, Seongjae Cho, Dong Hua Li, Jang-Gn Yun, Jung Hoon Lee, Gil Sung Lee, Yoon Kim, Won Bo Shim, Se Hwan Park, Wandong Kim, Hyungcheol Shin, and Byung-Gook Park*, "Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories," Japanese Journal of Applied Physics: Regular Papers, Vol. 49, No. 8, pp. 843011-843014, Aug. 2010.
20. Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, and Byung-Gook Park*, "Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices,"IEICE Transactions on Electronics, Vol. E93-C, No. 5, pp. 596-601, May. 2010.
19. Yoon Kim, Jang-Gn Yun, Seongjae Cho, and Byung-Gook Park*, "Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS)," 대한전자공학회지, Vol. 47, No. 2, pp. 102-107, Feb. 2010.
18. Seongjae Cho, Won Bo Shim, Il Han Park, Yoon Kim, and Byung-Gook Park*, "Highly Scalable 3-D NAND-NOR Hybrid-Type Dual Bit per Cell Flash Memory Devices with an Additional Cut-Off Gate," Journal of the Korean Physical Society, Vol. 56, No. 1, pp. 137-141, Jan. 2010.
17. Yoon Kim, Il Han Park, Seongjae Cho, Jang-Gn Yun, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Se Hwan Park, Dong Hua Li, Won Bo Shim, Wandong Kim, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park*, "A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical NOR Array Structure," IEEE Transactions on Nanotechnology, Vol. 9, No. 1, pp. 70-77, Jan. 2010.
2009
16. Hee-Sauk Jhon, Ickhyun Song, Jongwook Jeon, Minsuk Koo, Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin*, ”Low power size-efficient CMOS UWB low-noise amplifier design”, Microwave and Optical Technology Letters, Vol. 51, No. 2, pp. 494 - 496, Dec. 2009
15. Gil Sung Lee, Jung Hoon Lee, Il Han Park, Seongjae Cho, Jang-Gn Yun, Dong Hwa Li, Doo Hyun Kim, Yoon Kim, Se Hwan Park, Won Bo Shim, Wan Dong Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park*, "Cone-Type SONOS Flash Memory", IEEE Electron Device Letters, Vol. 30, No. 12 pp.1332-1334, Dec. 2009.
14. Seongjae Cho, Il Han Park, Yoon Kim, Se Hwan Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park*,“A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method,” IEEE Trans. Nanotechnol., Vol. 8, No. 5, pp. 595-602, Sep. 2009.
13. Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Daewoong Kang, Myoungrack Lee, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park*,“Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning,” IEEE Trans. Electron Dev., Vol.56, No. 8, pp. 1721-1728, Aug. 2009.
12. Hee-Sauk Jhon, Hakchul Jung, Jongwook Jeon, Minsuk Koo, Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin, ”Size efficient low-noise amplifier for 2.4 GHz ISM-band transceiver”, Microwave and Optical Technology Letters, Vol. 51, No. 10 pp. 2304 - 2308, Jul. 2009.
11. Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park*, “3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array,” IEICE Transactions on Electronics, Vol. E92-C, No. 5, pp. 653-658, May 2009.
10. Hee-Sauk Jhon, Hakchul Jung, Minsuk Koo, Ickhyun Song, Hyungcheol Shin*, ”0.7 V supply highly linear subthreshold low-noise amplifier design for 2.4 GHz wireless sensor network applications”, Microwave and Optical Technology Letters, Vol. 51, No. 5, pp. 1316 - 1320, Mar. 2009.
9. Minsuk Koo, Hakchul Jung, HeeSauk Jhon, Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin*, ”Investigation of frequency dependent sensitivity of noise figure on device parameters in 65 nm CMOS”, Journal Of Semiconductor Technology And Science, Vol. 9, No. 1, pp.61 - 66, Mar. 2009.
8. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park*, "A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node," IEEE Trans. Nanotechnol., vol. 8, pp. 111-115, Jan. 2009.
2008
7. Hee-Sauk Jhon, Ickhyun Song, Jongwook Jeon, Hakchul Jung, Minsuk Koo, Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin*, ”8 mW 17/24 GHz dual-band CMOS low-noise amplifier for ISM-band application”, Electronics Letters, Vol. 44, Iss. 23, pp. 1353 - 1354, Nov. 2008
6. Ickhyun Song, Hee-Sauk Jhon, Hakchul Jung, Minsuk Koo, Hyungcheol Shin*, ”A low power low noise amplifier with subthreshold operation in 130 nm CMOS technology”, Microwave and Optical Technology Letters, Vol. 50, No. 11, pp. 2762 - 2764, Nov. 2008
5. Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park*, "Fabrication and characterization of fin SONOS flash memory with separated double-gate structure," Solid-State Electron., vol. 52, pp. 1498-1504, October 2008.
4. Ickhyun Song, Hee-Sauk Jhon, Hakchul Jung, Minsuk Koo, Hyungcheol Shin*, ”Small size low noise amplifier with suppressed noise from gate resistance”, Microwave and Optical Technology Letters, Vol. 50, No. 9, pp. 2300 - 2304, June. 2008
3. Jang Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park*, “Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme,” IEICE Transactions on Electronics, Vol. E91-C, No. 5, pp. 742-746, May 2008.
2. Ickhyun Song, Minsuk Koo, Hakchul Jung, Hee-Sauk Jhon, Hyungcheol Shin*, ”Optimization of cascode configuration in CMOS low-noise amplifier”, Microwave and Optical Technology Letters, Vol. 50, No. 3, pp. 646 - 649, Jan. 2008
2007
1. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong-Duk Lee, and Byung-Gook Park*, "Formation of Si-Rich Silicon Nitride with Low Deposition Rate by Using LPCVD for Nanoscale Non-Volatile-Memory Application," Journal of the Korean Physical Society, Vol. 51, pp. S229~S233, December 2007.