Advanced Semiconductor Device&Circuit Laboratory
차세대 반도체 소자 및 회로 연구실
2024
162. 김정남, 김용우, 구민석, 김윤, "커패시티브 커플링을 통한 전압 합산 기반 행렬-벡터 곱 연산을 수행하는 Compute-In Memory 매크로", 2024 대한전자공학회 하계학술대회, Jun. 2024.
161. 안지훈, 구민석, 김윤, "3D vertical RRAM 기반 nvSRAM 및 CNN 구현 방법", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
160. 이선정, 김윤, "Graphene diffusion barrier를 이용한 PPXC 기반의 RRAM Crossbar Array", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
159. 김소중, 안지훈, 구민석, 김윤, "NAND 플래시 메모리와 DRAM이 융합된 NAD 메모리", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
158. 김용우, 김정남, 구민석, 김윤, "Design of UART Module and Digital Controlled Current Mirror in TSMC 28nm Process", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
157. 이원주, 김윤, 구민석, "NoC 기반 최적의 PIM 하드웨어 가속기 디자인 탐구를 위한 시뮬레이터", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
156. 김진혁, 구민석, 김윤, "Content Addressable Memory 동작 구현을 위한 주변 회로 시스템", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
155. 금건우, 안지훈, 구민석, 김윤, "로직 셀 기반 싱글 레벨 셀 낸드 플래시 메모리 상에서의 로직 연산 구현", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
154. 윤병호, 김보람, 안지훈, 구민석, 김윤, "CMOS Compatible Short-Term Memory Impletation", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
153. 전혜연, 구민석, 김윤, "스토캐스틱 비트 기반의 스파이킹 뉴럴 네트워크 설계", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
152. 김정남, 김용우, 구민석, 김윤, "Voltage Summation-Based Processing-In Memory SRAM Macro with 4-Bit Weight and 4-Bit Input Using Input-Bit Slicing Method", 제31회 한국반도체학술대회(KCS 2024), Jan. 2024.
2023
151. 김재성, 구민석, 김윤, "Spiking Neural Network with overflow retaining and underflow allowing", The 38th International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC) , June. 2023.
150. 김진혁, 방성진, 구민석, 김윤, "Implementation of Logic Operation in Embedded NOR Flash Memory for Processing-in-Memory Applications", The 38th International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC) , June. 2023.
149. 김정남, 김보람, 구민석, 김윤, "Energy Efficient Processing-In Memory Architecture with Voltage Summation-based Analog Vector-Matrix Multiplication", The 38th International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC) , June. 2023.
148. 이원주, 구민석, "실리콘 더블팁 3차원 적층형 저항변화메모리", 제30회 한국반도체학술대회(KCS 2023), Feb. 2023.
147. 김정남, 구민석, 김윤, "저전력 추론을 위한 용량성 커플링 기반의 뉴로모픽 아키텍처", 제30회 한국반도체학술대회(KCS 2023), Feb. 2023.
146. 김재성, 구민석, 김윤, "Spiking neural network 시스템 설계 및 I&F 뉴런회로의 선형성 개선", 제30회 한국반도체학술대회(KCS 2023), Feb. 2023.
145. 안지훈, 구민석, 김윤, "NAND 플래시 메모리와 SRAM이 융합된 NAS 메모리", 제30회 한국반도체학술대회(KCS 2023), Feb. 2023.
144. 최현석, 홍석원, 김윤, "균일한 두께의 그래핀 옥사이드 저항변화층을 가지는 RRAM 기반 시냅스 소자", 제30회 한국반도체학술대회(KCS 2023), Feb. 2023.
143. 안지훈, 구민석, 김윤, "Hybrid Memory combined with NAND Flash Memory and Static Random Access Memory", International Conference on Electronics, Information and Communication (ICEIC), Feb. 2023.
2022
142. 방성진, 안지훈, 구민석, 김윤, "임베디드 NOR 플래시 메모리에서의 병렬적 로직 연산 수행을 통한 processing-in-memory 구현",
제5회 반도체공학회 종합학술대회, Dec. 2022.
141. 김정남, 구민석, 김윤, "CTF 소자 기반의 채널 적층형 3차원 NOR형 시냅스 어레이 구조", 제5회 반도체공학회 종합학술대회, Dec. 2022.
140. 김조은, 김보람, 권희태, 구민석, 박동욱, 김윤, "Parylene-C 저항 변화 물질 기반의 RRAM crossbar array", 2022 반도체공학회 하계학술대회, Jul.2022.
139. 김정남, 구민석, 김윤, "저전력 추론을 위한 용량성 커플링 기반의 뉴로모픽 아키텍처", 2022 반도체공학회 하계학술대회, Jul.2022.
138. 박준성, 김재성, 채동혁, 김윤, 구민석, "교차 결합 인버터를 활용한 난수 생성 회로", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
137. 이용주, 장효원, 김보람, Swarup Biswas, 김윤, 김혁, "Tuning Operating Range of Organic Field Effect Transistors through Control of Gate Dielectric Layer Thickness", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
136. 최현석, 박준, 채동혁, 구민석, 김윤, "3차원 적층형 charge trap flash 소자의 적층 두께 제어를 통한 멀티레벨 컨덕턴스 변화 구현", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
135. 김조은, 김보람, 권희태, 채동혁, 구민석, 박동욱, 김윤, "Parylene-C 저항 변화 물질 기반의 RRAM crossbar array", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
134. 방성진, 안지훈, 채동혁, 구민석, 김윤, "Processing-In-Memory 응용을 위한 임베디드 NOR 플래시 메모리에서의 로직 연산 구현", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
133. 안지훈, 구민석, 김윤, "싱글 레벨 셀 낸드 플래시 메모리 상에서의 로직 연산 구현", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
132. 김재성, 박준성, 구민석, 김윤, "Input-splitting 구조가 적용된 spiking neural network 시스템 설계", 제29회 한국반도체학술대회(KCS2022), Jan. 2022.
2021
131. 최현석, 채동혁, 김윤, "전하 저장형 메모리 어레이를 이용한 컨볼루션 인공 신경망 구현", 제4회 반도체공학회 종합학술대회, Dec. 2021.
130. 안지훈, 구민석, 김윤, 강명곤, "Processing-in-memory logic operation implementation with eFlash", International Conference on Electronics, Information and Communication (ICEIC), Nov. 2021.
129. 안지훈, 김정남, 김조은, 구민석, 김윤, "임베디드 플래시 메모리 기반 인-메모리 컴퓨팅 로직 연산 구현", 2021 대한전자공학회 하계학술대회, Jul. 2021.
128. 김정남, 김윤, "Charge-Trap Flash 메모리 기반 채널 적층형 3차원 AND형 시냅스 어레이와 동작 방법", 2021 대한전자공학회 하계학술대회, Jul. 2021.
127. 김정남, 김윤, "개별 시냅스 가중치 조절을 위한 CTF 소자 기반 채널 적층형 3차원 시냅스 어레이의 동작 방법", 2021 반도체공학회 하계학술대회, Jul. 2021.
125. Ji-Hoon Ahn, Hyun-Seok Choi, Myounggon Kang and Yoon Kim, "Convolutional Neural Network Implementation with CTF Synaptic Device and ReLU Circuit," International Conference on Electronics, Information and Communication (ICEIC), Feb. 2021.
125. Jung Nam Kim, Hyun-Seok Choi, Boram Kim, Ji-Hoon Ahn, Jun Park, Yoon Kim, "CTF(Charge-Trap Flash)메모리 기반 채널 적층형 3차원 시냅스 어레이," 28th Korean Conference on Semiconductors, Jan. 2021.
124. 안지훈, 최현석, 김윤, "자체 적응형 뉴로모픽 시스템을 위한 온-칩 적응형 매칭 학습 방법," 28th Korean Conference on Semiconductors, Jan. 2021.
2020
123. 유병현, 김보람, 김혁, 차범성, 이승주, 김조은, 김윤, "Parylene-C 폴리머 기반 저전력 시냅스 소자의 개발," 대한전자공학회 추계학술대회, Nov. 2020.
122. 최현석, 김보람, 김정남, 박준, 안지훈, 김윤, "전하 저장형 메모리 어레이를 이용한 컨볼루션 인공 신경망 구현," 하계종합학술대회, June. 2020.
121. Boram Kim, Hyun-Seok Choi, Ji-Hoon Ahn and Yoon Kim, "Occasional Conductance Update without Re-write Method for SiNx-based Analog Synaptic Device," 27th Korean Conference on Semiconductors, Feb. 2020.
2019
120. 김윤, "뉴로모픽 반도체 기술 기초(invited talk)," 대한전자공학회 추계학술대회, Nov. 2019.
119. 김보람, 최현석, 김윤, "저항 변화 메모리의 비선형적 컨덕턴스 변화에 따른 패턴인식 정확도 연구," 하계종합학술대회, June. 2019
2018
118. Yu Jeong Park and Yoon Kim, "Synapse Device Based on Charge-Trap Flash memory for Neuromorphic Application," 2018 European Conference on Electrical Engineering & Computer Science (EECS 2018), Dec. 2018.
117. Boram Kim, Hui Tae Kwon, Won Joo Lee, Daehoon Wee and Yoon Kim, "Silicon Nitride Resistive Random-access Memory for Neuromorphic System with the Pattern Recognition," IEEE SILICON NANOELECTRONICS WORKSHOP 2018 (SNW 2018), June. 2018.
116. Daehoon Wee, Hui Tae Kwon, Won Joo Lee, Hyun-Seok Choi, Yu Jeong Park, Boram Kim and Yoon Kim, "Design of a Current Conveyor-Based Neuron Circuit for Neuromorphic Systems," IEEE SILICON NANOELECTRONICS WORKSHOP 2018 (SNW 2018), June. 2018.
115. Yoon Kim, "Emerging Three-dimensional Memory Technologies (invited talk)," 2018 China Semiconductor Technology International Conference (CSTIC), Mar. 2018.
114. 권희태, 이원주, 최현석, 위대훈, 박유정, 김 윤, "Self-Rectifying Resistive Random-Access Memory with a-Si/Si3N4 Bilayer," 25th Korean Conference on Semiconductors, Feb. 2018.
113. 이원주, 권희태, 최현석, 위대훈, 박유정, 김 윤, "Vertical Tunnel Field-Effect Transistor with Polysilicon Channel," 25th Korean Conference on Semiconductors, Feb. 2018.
112. Gwanho LEe, Yoon Kim, Jongwook Jeon, and Myounggon Kang, " Analysis of NLSB Effect depending on Cell Pattern and Bias Conditions in 3D NAND Flash Memory," International Conference on Electronics, Information and Communication (ICEIC), Jan. 2018.1214
111. Hyun-Seok Choi, Hui Tae Kwon, Yu Jeong Park, Daehoon Wee, Won Joo Lee, and Yoon Kim, "Analysis of STDP Characteristics of 3D Floating-Gate Synapse Device for Neuromorphic Applications," International Conference on Electronics, Information and Communication (ICEIC), Jan. 2018.
2017
110. Karthik Yogendra, Minsuk Koo, Kaushik Roy, ”Energy efficient computation using injection locked bias-field free spinhall nano-oscillator array with shared heavy metal”, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 25-26, 2017.
109. Yoon Kim, "Three-dimensional flash memory for data storage and neuromorphic applications (invited talk)," ITC-CSCC, July. 2017.
108. Daehoon Wee, Hui Tae Kwon, Hyun-Suk Choi, Won Joo Lee, Yu Jeong Park, and Yoon Kim, "U-shaped Reconfigurable Field-Effect Transistor," 24th Korean Conference on Semiconductors, Feb. 2017.
2016
107. Van Tan Tran, Younseong Song, Ki-Jae Jeong, Yoon Kim, and Jaebeom Lee, "Magnetic and Magnetoplasmonic Nanocomposites: Synthesis, Assemblies and Applications," 3rd International Symposium on Frontiers in Materials Science, Sep. 2016.
106. Yoon Hwae Hwang, Yoon Kim, and Dong Myeong Shin, "ZnO Nanorod/Graphene and Vertically Aligned Phase Nanopillars for Nanogenerator Applications," 3rd International Symposium on Frontiers in Materials Science, Sep. 2016.
105. Won Joo Lee, Hui Tae Kwon, Dae Hoon Wee, and Yoon Kim, "Tunnel Fin Field-Effect Transistor with Asymmetric Gate," Nano Korea, Jul. 2016.
104. Myounggon Kang, Won Joo Lee, and Yoon Kim, "Reconfigurable U-shape Tunnel FET," ITC-CSCC, Jul. 2016.
103. Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy, ”Computing with coupled spin torque nano oscillators”, Asia and South Pacific Design Automation Conference (ASP-DAC), January 25-28, 2016.
2015
2014
102. Joo Yun Seo, Yoon Kim, Do-Bin Kim, and Byung-Gook Park, "A new programming method to alleviate the program speed variation for three-dimensional channel stacked array architecture," Korean Conference on Semiconductors, pp. 80-80, Feb. 2014.
2013
101. Joonho Gil, Ji-Hoon Kim, Chun Suk Kim, Chulhyun Park, Jungsu Park, Hyejin Park, Hyeji Lee, Sung-Jae Lee, Young-Ho Jang, Minsuk Koo, Yong Won Kwon, Inho Song, ”A fully-integrated low-power high-coexistence 2.4-GHz ZigBee transceiver for biomedicai applications”, IEEE MTT-S International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications (IMWS-BIO),
December 09-11, 2013.
100. Wandong Kim, Joo Yun Seo, Yoon Kim, Se Hwan Park, Sang-Ho Lee, Myung Hyun Baek, Jong-Ho Lee, and Byung-Gook Park, "Channel-Stacked NAND flash memory with layer selection by multi-level operation (LSM)," IEEE International Electron Devices Meeting, pp. 3.8.1-3.8.4, Dec. 2013.
99. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, Sang-Ho Lee, and Byung-Gook Park, "Channel selection by multi level operation of string select line in 3D channel stacked NAND flash memory array," 한국반도체학술대회, pp. WE3-K-3-, Feb. 2013.
98. Joo Yun Seo, Sang-Ho Lee, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, and Byung-Gook Park, "A study on gate-all-around (GAA) polycrystalline silicon channel SONOS flash memory," IEEE International NanoElectronics Conference, pp. 69-71, Jan. 2013.
2012
97. Won Bo Shim, Seunghyun Kim, Yoon Kim, Se Hwan Park, Sungjun Kim, Euyhwan Park, and Byung-Gook Park, "Bitline separated gated multi-bit (BS-GMB) SONOS for high density flash memory," IEEE NANO, pp. 7927-, Aug. 2012.
96. Seunghyun Kim, Yoon Kim, and Byung-Gook Park, "Investigation of gate stacked array (GSTAR) for 3D NAND flash memory," International Technical Conference on Circuits/Systems, Computers and Communications, pp. B-W2-02-, Jul. 2012.
95. Do-Bin Kim, Yoon Kim, Seunghyun Kim, and Byung-Gook Park, "Investigation of read and program disturbance caused by programmed adjacent cell in NAND flash memory array,"International Technical Conference on Circuits/Systems, Computers and Communications, pp. B-W2-01-, Jul. 2012.
94. Joo Yun Seo, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array," Silicon Nanoelectronics Workshop, pp. 19-20, Jun. 2012.
93. Do-Bin Kim, Yoon Kim, Se Hwan Park, Wandong Kim, Joo Yun Seo, Seunghyun Kim, and Byung-Gook Park, "Control effect of new optimized structure of planar thin floating gate (FG) NAND flash to fringing field," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devieces, pp. 50-51, Jun. 2012.
92. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, and Byung-Gook Park, "가상 Source/Drain을 갖는 NAND 플래시 메모리에서 gate length 변동에 의한 문턱 전압 및 On-cell 전류 변동을 완화시키는 방법에 관한 연구," 하계종합학술대회, pp. 48-49, Jun. 2012.
91. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, Seunghyun Kim, and Byung-Gook Park, "Erase Speed Enhancement by Using SiGe Drain in 3D Stacked NAND Flash Memory," Korean Conference on Semiconductors, pp. 475-476, Feb. 2012.
90. Wandong Kim, Seunghyun Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, and Byung-Gook Park, "Layer Selection by Multi Level Operation (LSM) of String Select Line in 3D Stacked NAND Flash Memory," Korean Conference on Semiconductors, pp. 473-474, Feb. 2012.
89. Joo Yun Seo, Yoon Kim, Se Hwan Park, Wandong Kim, and Byung-Gook Park, "Investigation of Poly Depletion Effect in 3D stacked NAND flash memory," International Conference on Electronics, Information and Communication, pp. 4-5, Feb. 2012.
88. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, and Byung-Gook Park, "Variation of Threshold Voltage and ON Current Caused by Gate Length and Nanowire Diameter Fluctuation in Junctionless 3D NAND Flash Memory," International Conference on Electronics, Information and Communication, pp. 283-284, Feb. 2012.
2011
87. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, Do-Bin Kim, Seunghyun Kim, and Byung-Gook Park, "Investigation of Self Boosting Disturbance Induced by Channel Coupling in 3D Stacked NAND Flash Memory," International Semiconductor Device Research Symposium,
pp. 1-2, Dec. 2011.
86. Yoon Kim, Se Hwan Park, Wandong Kim, Joo Yun Seo, and Byung-Gook Park, "Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory," International Semiconductor Device Research Symposium, pp. 1-2, Dec. 2011.
85. Yoon Kim, Se Hwan Park, Wandong Kim, Joo Yun Seo, and Byung-Gook Park, "3차원 적층 NAND 플래시 메모리의 설계 및 특성 분석," 대한전자공학회 추계학술대회, pp. 129-132, Nov. 2011.
84. Wandong Kim, Yoon Kim, Se Hwan Park, Joo Yun Seo, and Byung-Gook Park, "Variation of Threshold Voltage and ON Cell Current induced by Word Line Length Fluctuation with Technology Node Scaling in Virtual Source/Drain NAND Flash Memory," NANO Korea, pp. P1101_177-P1101_177, Aug. 2011.
83. Won Bo Shim, Jung Hoon Lee, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Se Hwan Park, Joo Yun Seo, and Byung-Gook Park, "Design of Gated Twin-Bit (GTB) NAND Flash Memory Considering Gate Induced Drain Leakage (GIDL) Current," International Technical Conference on Circuits/Systems, Computers and Communications, pp. 308-309, Jun. 2011.
82. Jung Han Lee, Yoon Kim, Kwon-Chil Kang, Joung-Eob Lee, Kyung Wan Kim, and Byung-Gook Park, "Single Electron Transistor with P-type Sidewall Spacer Gates and SONOS Structure," International Technical Conference on Circuits/Systems, Computers and Communications, pp. 310-311, Jun. 2011.
81. Doo-Hyun Kim, Gil Sung Lee, Dong Hua Li, Yoon Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Retention Characteristics of 3D GAA(Gate-all-around) Charge Trap Flash Memory," Silicon Nanoelectronics Workshop, pp. 49-50, Jun. 2011.
80. Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)," Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 284-287, Jun. 2011.
79. Joo Yun Seo, Yoon Kim, Se Hwan Park, Wandong Kim, and Byung-Gook Park, "Compact Bit-line STacked ARray(STAR)," 하계종합학술대회, pp. 358-359, Jun. 2011.
2010
78. Won Bo Shim, Se Hwan Park, Jung Hoon Lee, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Wandong Kim, and Byung-Gook Park, "적층형 낸드 플래시 메모리에서 절연막 두께에 따른 게이트 간의 누설 전류에 관한 연구," 대한전자공학회 추계학술대회, pp. 32-33, Nov. 2010.
77. Dong Hua Li, Yoon Kim, Gil Sung Lee, Doo-Hyun Kim, Jung Hoon Lee, and Byung-Gook Park, "Charge Trapping and Memory Behaviors of the Ultra-thin SiN Layers," International Conference on the Physics of Semiconductors, pp. 1102-1102, Jul. 2010.
76. Gil Sung Lee, Doo-Hyun Kim, Jang-Gn Yun, Jung Hoon Lee, Yoon Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "A New Cone-Type 1T DRAM Cell," Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 23-25, Jul. 2010.
75. Yoon Kim, Jang-Gn Yun, Jung Hoon Lee, Gil Sung Lee, Se Hwan Park, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect," Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 217-220, Jul. 2010.
74. Doo-Hyun Kim, Gil Sung Lee, Seongjae Cho, Jung Hoon Lee, Jang-Gn Yun, Dong Hua Li, Yoon Kim, Se Hwan Park, Won Bo Shim, Wandong Kim, and Byung-Gook Park, "Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect," Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 37-40, Jul. 2010.
73. Wandong Kim, Dae Woong Kwon, Seongjae Cho, Dong Hua Li, Jang-Gn Yun, Jung Hoon Lee, Yoon Kim, Doo-Hyun Kim, Gil Sung Lee, Se Hwan Park, Won Bo Shim, and Byung-Gook Park, "Investigation of Current Degradation Induced by Silicide Source/Drain in the nanowire NAND Flash Memory," 하계 종합 학술발표회 논문집, pp. 489-490, Jun. 2010.
72. Doo-Hyun Kim, Yoon Kim, Gil Sung Lee, Jung Hoon Lee, Seongjae Cho, Jang-Gn Yun, Dong Hua Li, and Byung-Gook Park, "Investigation of Width Dependent Retention Characteristics with GAA(Gate-All-Around) SONOS structure," 하계 종합 학술발표회 논문집, pp. 483-484, Jun. 2010.
71. Gil Sung Lee, Yoon Kim, and Byung-Gook Park, "Research of Memory Characteristics of GAA(Gate All Around) and DG(Double Gate) Type Bit Line Stacked Array," 하계 종합 학술발표회 논문집, pp. 714-715, Jun. 2010.
70. Yoon Kim, Jang-Gn Yun, Se Hwan Park, Wandong Kim, and Byung-Gook Park, "Study of 3-dimentional stacked vertical NAND falsh memory," 하계 종합 학술발표회 논문집, pp. 730-733, Jun. 2010.
69. Jang-Gn Yun, Yoon Kim, Se Hwan Park, Jong-Ho Lee, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Vertical Crosstalk Phenomenon (VCP) Among Neighboring Cells in 3D Stacked NAND Flash Memory," 하계 종합 학술발표회 논문집, pp. 716-718, Jun. 2010.
68. Seongjae Cho, Yoon Kim, Won Bo Shim, Dong Hua Li, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Highly Scalable Vertical Bandgap-Engineered NAND Flash Memory,"Device Research Conference, pp. 265-266, Jun. 2010.
67. Wandong Kim, Jung Hoon Lee, Seongjae Cho, Jang-Gn Yun, Se Hwan Park, Yoon Kim, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Won Bo Shim, and Byung-Gook Park, "Arch SONOS NAND Flash Memory Array with Improved Virtual Source and Drain Performance Due to the Field Concentration Effect," Korean Conference on Semiconductors, pp. 55-56, Feb. 2010.
66. Jang-Gn Yun, Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Yoon Kim, Dong Hua Li, Se Hwan Park, Won Bo Shim, Garam Kim, and Byung-Gook Park, "Three Dimensional Stacked Bit-line NAND Flash Array and Inter-layer Interference," Korean Conference on Semiconductors, pp. 53-54, Feb. 2010.
65. Doo-Hyun Kim, Gil Sung Lee, Jung Hoon Lee, Seongjae Cho, Jang-Gn Yun, Dong Hua Li, Yoon Kim, Se Hwan Park, Won Bo Shim, Wandong Kim, and Byung-Gook Park, "VT decay mechanisms in SONOS flash memory retention mode including trapped charge redistribution effect," Korean Conference on Semiconductors, pp. 485-486, Feb. 2010.
64. Dong Hua Li, Yoon Kim, and Byung-Gook Park, "Comparative Analysis of Trap-based Program/Erase Behaviors with Tunnel Dielectric for SONOS Flash Memory," IEEE International NanoElectronics Conference, pp. 3-8, Jan. 2010.
2009
63. 김윤, 이길성, 조성재, 박일한, 윤장근, 이정훈, 이동화, 김두현, 심원보, 김완동, 박병국, "Virtual Source/Drain을 가지는 Folded NAND Flash Memory 영향", 2009 IEEK Summer conference, Jeju, Korea, pp. 397-398, July 8-10, 2009.
62. Dong Hua Li, Il Han Park, Jang-Gn Yun, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Se Hwan Park, Won Bo Shim, Wandong Kim, Seongjae Cho, and Byung-Gook Park, "Scaling Behaviors of Silicon Nitride Layer for Charge Trapping Memory", AVS 56th International Symposium and Exhibition, San Jose, USA, EM-TuP18, Nov. 8-13, 2009.
61. 심원보, 이정한, 조성재, 윤장근, 이정훈, 이동화, 이길성, 김두현, 김윤, 박세환, 김완동, 박병국, "3차원 구조의 차단 게이트를 이용한 2-비트 낸드플래시 메모리의 pinch-off 현상에 따른 최적 읽기 구동 방법", 2009 IEEK fall conference, Seoul, Korea, pp.49-50, Nov. 28, 2009.
60. Seongjae Cho, Yoon Kim, Jang-Gn Yun, Jung Hoon Lee, Won Bo Shim, and Byung-Gook Park, "Dependence of Program and Erase Speeds on Bias Conditions for Fully Depleted Channel of Vertical NAND Flash Memory Devices", 10th Annual Non-Volatile Memory Technology Symposium, Portland, USA, pp.8-2 Oct. 25-28, 2009.
59. 김윤, 이길성, 조성재, 박일한, 윤장근, 이정훈, 이동화, 김두현, 심원보, 김완동, 박병국, "Virtual Source/Drain을 가지는 Folded NAND Flash Memory 영향", 2009 IEEK Summer conference, Jeju, Korea, pp. 397-398, July 8-10, 2009.
58. 김완동, 이동화, 박일한, 조성재, 윤장근, 이정훈, 김윤, 김두현, 이길성, 박세환, 박병국, "실리콘 몸체 두께 변동이 가상 Source/Drain을 갖는 Double Gate NAND 플래시 메모리에 미치는 영향", 2009 IEEK Summer conference, Jeju, Korea, pp. 387-388, July 8-10, 2009.
57. 이길성, 김윤, 박병국, "고집적 원통형 구조의 전계 특성에 대한 연구", 2009 IEEK Summer conference, Jeju, Korea, pp. 389-390, July 8-10, 2009.
56. 이동화, 박일한, 윤장근, 이정훈, 김두현, 이길성, 김윤, 박세환, Syed Atif Pervez, 박병국, "Bandgap Engineering 도입하여 향상된 홀 터널링 특성을 구현한 SONOS 플래쉬 메모리 소자", 2009 IEEK Summer conference, Jeju, Korea, pp. 393-394, July 8-10, 2009.
55. Yoon Kim, Seongjae Cho, Jang-Gn Yun, Il Han Park, Gil Sung Lee, Doo-Hyun Kim, Dong Hua Li, Se Hwan Park, Wandong Kim, Wonbo Shim, and Byung-Gook Park, "Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory", 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, 3B.3, June 24-26, 2009.
54. Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, and Byung-Gook Park, "Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices", 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, 3B.8, June 24-26, 2009.
53. Seongjae Cho, Il Han Park, Jung Hoon Lee, Yoon Kim, Hyungcheol Shin and Byung-Gook Park, "Analytical Modeling of Radial Channel Potential and Surface Charge Density of Cylindrical MOSFET Devices under Arbitrary Surface Potentials", The 24nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea, pp. 1213-1214, July 5-8, 2009.
52. Wandong Kim, Il Han Park, Jang-Gn Yun, Jung Hoon Lee, Se-Hwan Park, Yoon Kim, Dong Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won Bo Sim, Jong-Duk Lee, and Byung-Gook Park, "Impact of Three-dimensional Device Structures on NAND Flash Memory with Inversion Type Source and Drain", 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 69-70, June 13-14, 2009.
51. Won Bo Shim, Il Han Park, Seongjae Cho, Jung Hoon Lee, Jang-Gn Yun, Dong Hua Li, Gil Sung Lee, Doo Hyun Kim, Yoon Kim, Se Hwan Park, Wandong Kim, and Byung-Gook Park, "Device Structure and Operation of Stacked Vertical AND array for High Density Flash Memory", 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 79-80, June 13-14, 2009.
50. Doo-Hyun Kim, Yoon Kim, Il Han Park, Jung Hoon Lee, Seongjae Cho, Jang-Gn Yun, Dong Hua Li, Gil Sung Lee, Se Hwan Park, Won Bo Shim and Byung-Gook Park, "Simulation of Retention Characteristics in Double-Gate Structure SONOS Flash Memory with Body Doping Concentration", 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 71-72, June 13-14, 2009.
49. Dong Hua Li, Il Han Park, Seongjae Cho, Jang-Gn Yun, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung lee, Yoon Kim, Se Hwan Park, Won Bo Shim, and Byung-Gook Park, "Study of Tunneling Oxides Fabricated by Different Processes and Their Effects on Memory Characteristics of SONOS Capacitors", E-MRS 2009 Spring Meeting, Congress Center, Strasbourg, France, I15-11, June 8-12, 2009.
48. Dong Hua Li, Il Han Park, Seongjae Cho, Jang-Gn Yun, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung lee, Yoon Kim, Se Hwan Park, Won Bo Shim, Wandong Kim, and Byung-Gook Park, "Effects of Equivalent Oxide Thickness on Bandgap-Engineered SONOS Flash Memory", 2009 IEEE Nanotechnology Materilas and Devices Conference, Traverse City, Michigan, USA, pp.255-258, June 2-5, 2009.
47. 이정훈, 조성재, 박일한, 윤장근, 이동화, 김두현, 이길성, 김윤, 박병국, "PCI Consideration of Multiple Dielectric Layer's Equivalent Oxide Thickness(EOT) in a Cylindrical Structure", The 16th Korean Conference on Semiconductors, Deajeon, Korea, pp. 746-747, Feb. 18-20, 2009.
46. 김윤, 윤장근, 박일한, 조성재, 이정훈, 이동화, 김두현, 이길성, 심원보, 김완동, 신형철, 박병국, "PCI Phenomenon for Sub 30nm Vertical Multi-bit SONOS Flash Memory", The 16th Korean Conference on Semiconductors, Deajeon, Korea, pp. 535-536, Feb. 18-20, 2009.
45. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Doo-Hyun Kim, Yoon Kim, Dong-Hua Lee, Se-Hwan Park, Won-Bo Sim, Wandong Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, "Multi-Bit Gated-Diode Flash Memory", The 16th Korean Conference on Semiconductors, Deajeon, Korea, pp. 300-301, Feb. 18-20, 2009.
44. Seongjae Cho, Yoon Kim, Se Hwan Park, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Highly Scalable Three-Dimensional Two-Bit NAND-Type Flash Memory Device with Additional Cut-off Gate", The 16th Korean Conference on Semiconductors, Deajeon, Korea, pp. 20-21, Feb. 18-20, 2009.
2008
43. Dong Hua Li, Seongjae Cho, Il Han Park, Jang-Gn Yun, Jung Hoon Lee, Gil Sung Lee, Doo-Hyun Kim, Yoon Kim, Se-Hwan Park, Won Bo Sim, Jong Duk Lee, and Byung-Gook Park, "Charge Trapping Characteristics of SONOS Capacitors with Control Gates of Different Work Functions during Program/Erase Operation," 2008 Materials Research Society, Boston, USA, A11.1, December 1-5, 2008.
42. Hee-Sauk Jhon, Hakchul Jung, Minsuk Koo, Hyungcheol Shin, ”A concurrent dual-band CMOS low-noise amplifier for ISM-band application”, IEEE International SoC Design Conference, November 24-25, 2008.
41. 윤장근, 박일한, 조성재, 이정훈, 이길성, 김두현, 김윤, 이동화, 박세환, 심원보, 김완동, 신형철,이종덕, 박병국, "적층된 수직 채널 NOR 플래시 메모리의 비선택 비트라인 전위 부양 효과," 2008 IEEK Fall Conference, Seoul, Korea, pp.389-390, November 29, 2008.
40. 조성재, 윤장근, 김윤, 이동화, 이종덕, 박병국, "채널 길이와 도핑 농도에 따른 낸드 플래시 메모리 소자의 결합비 의존성 연구," 2008 IEEK Fall Conference, Seoul, Korea, pp.381-382, November 29, 2008.
39. Minsuk Koo, Hakchul Jung, Ickhyun Song, Hee-Sauk Jhon, Hyungcheol Shin, ”A 2.4 GHz CMOS ultra low power low noise amplifier design with 65 nm CMOS technology”, IEEE International Conference on Solid-State and Integrated- Circuit Technology, October 20-23, 2008.
38. Hakchul Jung, Hee-Sauk Jhon, Ickhyun Song, Minsuk Koo, Hyungcheol Shin, ”Design optimization of a 10 GHz Low Noise Amplifier with gate drain capacitance consideration in 65 nm CMOS Technology”, IEEE International Conference on Solid-State and Integrated-Circuit Technology, October 20-23, 2008.
37. Seongjae Cho, Yoon Kim, Se Hwan Park, Jong Duk Lee, Hyungcheol Shin and Byung-Gook Park, "Design Considerations for Gated Twin-Bit (GTB) Nonvolatile Memory Device Regarding Leakage Current," The 2nd IEEE Nanotechnology Materials and Devices Conference, Kyoto, Japan, pp.208, October 20-22, 2008.
36. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Dong Hua Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Se-Hwan Park, Won Bo Sim, Wandong Kim, Jong Duk Lee and Byung-Gook Park, "Stacked Vertical Channel (SVC) NOR Flash Memory," The 2nd IEEE Nanotechnology Materials and Devices Conference, Kyoto, Japan, pp.151, October 20-22, 2008.
35. Yoon Kim, Gil-Seong Lee, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, " 3-dimensional Terraced NAND (3D TNAND) Flash Memory, " 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Sapporo, Japan, pp.85-88, July 9-11, 2008.
34. Gil Sung Lee, Doo Hyun Kim, Il Han Park, Jung Hoon Lee, Seongjae Cho, Jang-Gn Yun, Dong Hua Li, Yoon Kim, Se Hwan Park, Won Bo Shim, Jong Duk Lee and Byung-Gook Park, " Fabrication Process of Cone SONOS Memory Structure," 2008 The 9th International Conference on Electronics, Information, and Communication, Tashkent, Uzbekistan, pp.1017-1020, June 24-27, 2008.
33. Doo-Hyun Kim , Gil Sung Lee, Jung Hoon Lee, Il Han Park, Seong-Jae Cho, Jang-Gn Yun, Dong Hua Li, Yoon Kim, and Byung-Gook Park, " Retention Model of NAND-type Nitride-Based Charge Trapping Flash Memory," 2008 The 9th International Conference on Electronics, Information, and Communication, Tashkent, Uzbekistan, pp.1033-1036, June 24-27, 2008.
32. Jung Hoon Lee, Il Han Park, Seongjae Cho, Gil Seong Lee, Doo Hyun Kim, Jang Gn Yun, Yoon Kim, Jong Duk Lee, Byung-Gook Park, " Enhanced Program/Erase Characteristic of Arch Shaped SONOS Flash Memory," 2008 The 9th International Conference on Electronics, Information, and Communication, Tashkent, Uzbekistan, pp.1029-1032, June 24-27, 2008.
31. Yoon Kim, Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Se-Hwan Park, Dong Hua Lee, Doo-Hyun Kim, Gil Sung Lee, Won Bo Sim, Jong-Duk Lee, and Byung-Gook Park, " Locally-Separated Vertical Channel SONOS Flash Memory (LSVC SONOS) for Multi-Storage and Multi-Level Operation," IEEE 2008 Silicon Nanoelectronics Workshop, Honolulu, USA, P2-33, June 15-16, 2008.
30. Jang-Gn Yun, Il Han Park, Jung Hoon Lee, Se-Hwan Park, Yoon Kim, Dong Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won Bo Sim, Jong-Duk Lee, and Byung-Gook Park, " Vertical Channel Double Split-Gate (VCDSG) Flash Memory," IEEE 2008 Silicon Nanoelectronics Workshop, Honolulu, USA, P2-29, June 15-16, 2008.
29. Ickhyun Song, Hakchul Jung, Hee-Sauk Jhon, Minsuk Koo, Hyungcheol Shin, ”24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization”, 電子情報通信学会技術研究報告. SDM, シリコ ン材料・デバイス, May. 2008.
28. Ickhyun Song, Hee-Sauk Jhon, Hakchul Jung, Minsuk Koo, Yehao Shen, Hyungcheol Shin, ”Low Power Ultrawideband Low Noise Amplifier Design Using 0.18-μm Mixed-Signal CMOS Process”, 대한전자공학회학술대회, May. 2008.
27. Gil Sung Lee, Il Han Park, Seongjae Cho, Jang-Gn Yun, Jung Hoon Lee, Dong Hua Li, Doo Hyun Kim, Yoon Kim, Se Hwan Park, Won Bo Shim, Jong Duk Lee and Byung-Gook Park, " Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure," IEEE 2008 Silicon Nanoelectronics Workshop, Honolulu, USA, P2-30, June 15-16, 2008.
26. 박일한, 조성재, 이정훈, 윤장근, 김두현, 이길성, 이동화, 박세환, 김윤, 심원보, 이종덕, 박병국, "Vertical-AND Array with Spacer Gate for High Density Flash Memories," The 15th Korean Conference on Semiconductors, Pyeongchang, Korea, pp. 411-412, Feb. 20-22, 2008.
25. Gil Sung Lee, Jung Hoon Lee, Il Han Park, Seong-Jae Cho, Jang-Gn Yun, Doo Hyun Kim, Dong Hua Li, Yoon Kim, Se Hwan Park, Won Bo Sim, Jong Duk Lee and Byung-Gook Park, "Fabrication of Cone SONOS Memory for Better Program/Erase Characteristics," The 15th Korean Conference on Semiconductors, Pyeongchang, Korea, pp. 55-56, Feb. 20-22, 2008.
24. Se Hwan Park, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, SeongJae Cho, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park, "Design and Simulation of Folded Split Gate SONOS Memory," The 15th Korean Conference on Semiconductors, Pyeongchang, Korea, pp. 437-438, Feb. 20-22, 2008.
23. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Dong Hua Lee, Se-Hwan Park, Won Bo Sim, Jong-Duk Lee, and Byung-Gook Park, "Double-Recessed channel (DRC) flash memory," The 15th Korean Conference on Semiconductors, Pyeongchang, Korea, pp. 49-50, Feb. 20-22, 2008.
2007
22. Il Han Park, Seongjae Cho, Jung Hun Lee, Gil Seong Lee, Doo-Hyung Kim, Jang-Gn Yoon, Yoon Kim, Sangwoo Kang, Il Hwan Cho, Daewoong Kang, Jong-Duk Lee, and Byung-Gook Park, "Vertical AND (V-AND) Array: High Density, High Speed, and Reliable Flash Array," 2007 International Semiconductor Device Research Symposium, Maryland, USA, December 12-14, 2007.
21. Jang-Gn Yun, Yoon Kim, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Dong Hwa Lee, Se Hwan Park, Wonbo Sim, Jong-Duk Lee, and Byung-Gook Park, "Fin Flash Memory Cells with Separated Double Gates," 2007 International Semiconductor Device Research Symposium, Maryland, USA, December 12-14, 2007.
20. Ickhyun Song, Minsuk Koo, Hakchul Jung, Sanghoon Lee, Shen Yehao, Hee-Sauk Jhon, Hyungcheol Shin, ”Noise Interpolation of MOSFET in Moderate Inversion and Its Verification in Low Noise Amplifier”, 대한전자공학회 추계학술대회, 2007
19. Hee-Sauk Jhon, Ickhyun Song, Yeonam Yun, Minsuk Koo, Hakchul Jung, Hyungcheol Shin, ”Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors”, 대한전자공학회 추계학술대회, 2007
18. 김윤, 윤장근, 박일한, 조성재, 이정훈, 이길성, 김두현, 이동화, 심원보, 신형철, 이종덕, 박병국, "수직 채널을 갖는 4-비트 SONOS 노어 플래시 메모리," 2007 IEEK Fall Conference, pp.441-442, Seoul, Korea, November 24, 2007.
17. 이정훈, 박일한, 조성재, 윤장근, 이동화, 김윤, 김두현, 이길성, 박세환 심원보, 박병국, "나노 소자에 적용 가능한 곡면의 실리콘 핀 (Fin) 제작 공정," 2007 IEEK Fall Conference, pp.349-350, Seoul, Korea, November 24, 2007.
16. 윤장근, 박일한, 조성재, 이정훈, 김두현, 이길성, 김윤, 이동화, 박세환, 심원보, 이종덕, 박병국, "수직 분할 게이트 구조의 2-비트 리세스 채널 SONOS 메모리," 2007 IEEK Fall Conference, pp.345-346, Seoul, Korea, November 24, 2007.
15. 박일한, 이정훈, 윤장근, 조성재, 김두현, 이길성, 이동화, 박세환, 김윤, 이종덕, 박병국, "20 nm 급 소자 제작을 위한 sidewall spacer patterning 공정," 2007 IEEK Fall Conference, pp.335-336, Seoul, Korea, November 24, 2007.
14. 이동화, 박일한, 조성재, 윤장근, 이정훈, 이길성, 김두현, 김윤, 박세환, 심원보, 박병국, "Trapping 저장 노드의 두께에 따른SONOS flash 메모리 소자의 프로그램 특성," 2007 IEEK Fall Conference, pp.445-446, Seoul, Korea, November 24, 2007.
13. Ickhyun Song, Minsuk Koo, Hakchul Jung, Hee-Sauk Jhon, Hyungcheol Shin, ”Analytic approach to power-constrained CMOS low-noise amplifier design with figure of merit consideration”, IEEE TENCON, Oct 30-02, 2007.
12. 이정훈, 박일한, 조성재, 이길성, 김두현, 윤장근, 김윤, 이동화, 박세환, 박병국, " Benefits of Arch Structure in Non-volatile Charge Trap Flash Memory," 2007년도 대한전자공학회 하계종합학술대회, 부산, pp. 739-740, 7월11일-13일, 2007.
11. 조성재, 박일한, 이정훈, 윤장근, 김두현, 이길성, 김윤, 이동화, 신형철, 이종덕, 박병국, " 신뢰성 있는 동작을 위한 수직 구조 플래시 메모리의 공정 및 전압 조건의 최적화 연구," 2007년도 대한전자공학회 하계종합학술대회, 부산, pp. 743-744, 7월11일-13일, 2007.
10. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong-Duk Lee, and Byung-Gook Park, "Characterization of 2-bit Recessed Channel Memory with Lifted Charge Trapping Node Scheme", The 22nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2007), Busan, Korea, vol. 2, pp. 437-438, July 8-11, 2007.
9. Yoon Kim, Jang-Gn Yun and Byung-Gook Park, "4-bit FinFET SONOS Flash Memory-Optimization of Structure and 3D Numerical Simulation", 2007 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Gyeongju, Korea, pp. 229-232, June 25-27, 2007.
8. Ickhyun Song, Minsuk Koo, Hee-Sauk Jhon, Hyungcheol Shin, ”CMOS low-noise amplifer with noise suppression technique from gate resistance”, 電子情報通信学会技術研究報告. ED, 電子デバイス(AWAD), June 25-27, 2007.
7. Il Han Park, Se Hwan Park, Seongjae Cho, Jung Hun Lee, Gil Sung Lee, Doo Hyun Kim, Jang Geoun Yoon, Yoon Kim, Jong Duk Lee, and Byung-Gook Park, "Self-Aligned Vertical Channel Split-Gate (VCSG) SONOS Flash Memory with Stair-Channel Structure Fabricated by Two-Step Si Etching Process", IEEE 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 109-110, June 10-11, 2007.
6. Gil Sung Lee, Il Han Park, Seong Jae Cho, Jang-Gn Yun, Jung Hoon Lee, Dong Hwa Lee, Doo Hyun Kim, Yoon Kim, Se Hwan Park and Byung-Gook Park, "Program Characteristic Improvement in Cone Type SONOS Memory Structure", IEEE 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 97-98, June 10-11, 2007.
5. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Doo-Hyun Kim, Yoon Kim, Jong-Duk Lee, and Byung-Gook Park, "2-bit Recessed Channel Nonvolatile Memory Device with Lifted Charge Trapping Node Scheme", IEEE 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 99-100, June 10-11, 2007.
4. Jang-Gn Yun, Yoon Kim, Il Han Park, Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Doo-Hyun Kim, Dong Hua Lee, Se-Hwan Park, Jong-Duk Lee, and Byung-Gook Park, "Study of Programming Characteristics of 4-bit SONOS Flash Memory Using 3-Dimensional Transient Simulation", 2nd International Conference on Memory Technology and Design, Giens, France, pp. 81-84, May 7-10, 2007.
3. Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong-Duk Lee, and Byung-Gook Park, "Formation of Si-rich Silicon Nitride with Low Deposition Rate for NanosCALe Nonvolatile Memory Application", The 14th Korean Conference on Semiconductors, Seogwipo, Korea, pp. 585-586, Feb. 8-9, 2007.
2006
2. Jung-Hoon Lee, Hyun-Woo Kim, Il Han Park, Seongjae Cho, Gil Seong Lee, Doo Hyun Kim, Jang Gn Yun, Yoon Kim, Jong Duk Lee, Byung-Gook Park, and Euijoon Yoon, "Low-pressure, low-temperature hydrogen annealing for nanoscale silicon fin rounding", IEEE Nanotechnology Materials and Devices Conference 2006, Gyeongju, Korea, pp. 638-639, October 22-25, 2006.
1. Doo-Hyun Kim, Jung Hoon Lee, Il Han Park, Sung Jae Cho, Gil SUNG Lee, Yoon Kim, Jae Young Song, Jin Ho Kim, Dong-Wook Park, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Silicon Corner Rounding for Nano-Scale Non-volatile Memory (NVM) Using Conventional Thermal Oxidation," International Conference on Electronics, Information, and Communication 2006, Ulaanbaatar, Mongolia, pp. 137-140, June 27-28, 2006.